Transmit Control Register 2 Configuration - Texas Instruments OMAP5910 Technical Reference Manual

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Table 7–84. Transmit Control Register 2 Configuration (ARM_Write(0x0001) => XCR2)

Configuration Value

Sample Rate Generator Configuration (SRGR[1,2])

Interrupt Flag Configuration and Clear (ILR, ITR, MIR)

Take out of Reset for Transmit and Receive Starting (SPCR[1,2])

ARM_Write(0x0001) => XCR2; set up XCR2 per below configuration.

Set single-phase frame

Don't care for single-phase frame

Set no companding data and transfer start with MSB first

Set FSX not ignore after the first resets the transfer

Set data delay as 1 bit

1) Configure the sample rate generator appropriately for CLKX and FSX. For

details, see TMS320C54x DSP Enhanced Peripherals Reference Set,

vol. 5, SPRA302.

2) Wait for two CLKSRG clocks.

3) ARM_Write SPCR2 or (0x0000 0040) → SPCR2;CLKG enable

4) Wait two CLKG clocks.

1) ARM_Write → ILR; set ILR appropriately for the interrupt handling priority.

2) ARM_Write ITR and (0xFFFF FFCF) → ITR; clear remained TX and RX

This setup is not needed after reset.

3) ARM_Write MIR and (0xFFFF FFCF) → MIR; enabled SPI TX and RX

1) ARM_write SPCR1 or (0x0001) → SPCR1; enabled receive port

2) ARM_write SPCR2 or (0x0001) → SPCR2; enabled transmit port

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