Mpu I/O Input Masking Timing - Texas Instruments OMAP5910 Technical Reference Manual

Figure 7–14. MPU I/O Input Masking Timing
CLK_32 KHz
MPUIO_IN(I)
GPIO_MASKIT(I)
GPIO_MASKIT_SS(I)
after 32 KHz resync
GPIOS_INT
NSTROBE
TIPB access cycle
debouncing period; the debouncing is then forced dynamically to 0 and the
interrupt is generated five cycles after the mask presence. You must decide
whether or not to mask these interrupts by maintaining or releasing the mask
activation.
When one detected edge is masked, the event is not reset when a GPIO_INT
register read occurs. Thus, when the mask becomes inactive, the correspond-
ing detected edge generates the gpios_int interrupt, and this interrupt is reset
on the next GPIO interrupt register (GPIO_INT) read, as shown in
Figure 7–14.
The mask is present two cycles before
the active edge on the MPUIO input;
consequently the debouncing is forced to
0 from the start and the IT must be
generated three cycles after the detected
edge.
When a GPIO interrupt is masked, the GPIO_INT register does not indicate
any active interrupt status if an edge occurs on the masked interrupt. However,
if an edge occurs while the GPIO interrupt is masked, the active interrupt status
is stored and an interrupt is sent to the interrupt handler as soon as that GPIO
interrupt is unmasked (enabled).
The IT is masked
during this period.
The GPIO_INT read
asynchronously resets
the gpios_int interrupt.
MPU Public Peripherals
MPU I/O
7-23