Emif Requests And Their Priorities - Texas Instruments OMAP5910 Reference Manual

DSP External Memory Interface
5.2.4 EMIF Requests
Table 14. EMIF Requests and Their Priorities
EMIF Requester
E bus
F bus
D bus
C bus
P bus
DMA controller
60 DSP Subsystem
The EMIF services the requests shown in Table 14. If multiple requests arrive
simultaneously, the EMIF prioritizes them as shown in the Priority column.
Priority Description
1 (highest) A write request from the E bus of the DSP core.
2 A write request from the F bus of the DSP core.
3 A read request from the D bus of the DSP core.
4 A read request from the C bus of the DSP core.
5 An instruction fetch request from the DSP core or instruction cache.
In the core, instructions are received on the P bus.
6 A write or read request from the DSP DMA controller.
As shown in Table 15, there is a subtle difference between dual data accesses
and long data accesses requested by the DSP core. The following two
instructions are examples of these access types:
ADD *AR0, *AR1, AC0
ADD dbl(*AR2), AC1
Both access types require two 16-bit data buses in the DSP core, but they
require different numbers of EMIF requests. A dual data access involves two
separate 16-bit values and, therefore, requires two EMIF requests. A long data
access involves a single 32-bit value and, therefore, a single EMIF request.
This EMIF request corresponds to the address bus used. For example, if a long
data read is performed, the DAB address bus is used, and the EMIF receives
a D-bus request.
; Dual data access. Two separate
; 16−bit values referenced by
; pointers AR0 and AR1.
; Long data access. One 32−bit
; value referenced by pointer AR2.
SPRU890A