Emiff Operation; Possible Sdram Configurations - Texas Instruments OMAP5910 Reference Manual

3.3.2

EMIFF Operation

Table 8.

Possible SDRAM Configurations

SPRU673
The low-priority queue order is:
J
MPU
H
H DSP
H Local bus
DMA (all channels including LCD)
H
The high-priority queue order is:
J
H DMA transfer involving LCD channel
H DSP
H Local bus
H DMA transfer involving channels other than LCD channel
Fixed priority is a special case of dynamic priority. To create a fixed priority,
-
all time-out registers must have a value of 0. This way any request made
goes into the high-priority queue after one clock cycle. Then the high-
priority queue provides a fixed priority.
The EMIFF controller can support up to two devices for up to 64M bytes of
memory. The following devices are supported:
256M bit, 128M bit, 64M bit
-
2 or 4 banks for 64M byte device
-
x8 or x16 data bus configurations
-
Table 8 shows the possible SDRAM configurations.
Memory Size Bus
(Bytes) Size
64M 1 x16
2 x 8
32M 1 x 16
2 x 8
16M 1 x 16
2 x 8
8M 1 x 16
4M 2 x 8
2M 1 x 16
Number of
Devices
Type of Device
1 512M bits organized in 32M x 16
2 256M bits organized in 32M x 8
1 256M bits organized in 16M x 16
2 128M bits organized in 16M x 8
1 128M bits organized in 8M x 16
2 64M bits organized in 8M x 8
1 64M bits organized in 4M x 16
2 16M bits organized in 2M x 8
1 16M bits organized in 1M x 16
Memory Interface Traffic Controller
Memory Interfaces
35