Dsp Subsystem Memory; Internal Memory Space - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Memory

3 DSP Subsystem Memory
3.1

Internal Memory Space

26 DSP Subsystem
The DSP subsystem requires access to three different types of memory:
program memory, data memory, and I/O memory. The DSP subsystem
architecture uses a unified program and data memory space composed of
memory internal and external to the DSP subsystem. Internal memory is made
up of tightly coupled memory blocks, whereas DSP external memory is
mapped to OMAP system memory. The DSP subsystem architecture provides
access to a maximum of 8M words (16M bytes) of program/data memory
space.
The DSP subsystem I/O memory space is separate from the data/program
memory space. The I/O space includes the configuration and data registers
for all peripherals accessible by the DSP subsystem.
The DSP subsystem memory consists of four types of tightly coupled
memories which provide the DSP core with maximum efficiency.
Dual-access RAM (DARAM)
-
The DARAM memory consists of 8 blocks of 8K bytes each. The DARAM
(64K bytes) can support up to two memory accesses into each RAM block
in one DSP core clock cycle. Accesses can be made from any internal
data, program, or DMA bus.
Single-access RAM (SARAM)
-
The SARAM memory consists of 12 blocks of 8K bytes each. The SARAM
(96K bytes) can support one memory access into each RAM block in one
DSP core clock cycle. This access can be a 32-bit value. Accesses can be
made from any internal data, program, or DMA bus.
Programmable dynamic ROM (PDROM)
-
The PDROM memory consists of 1 block of 32K bytes. The programmable
dynamic ROM (32K bytes) can support one memory read in one DSP core
clock cycle. This access can be a 32-bit value. Accesses can be made
from any internal data read or program bus.
The PDROM contains a program called a bootloader, which is executed by
the DSP core when it is taken out of reset. Depending on the boot mode
selected, the DSP core will either branch to an internal or DSP external
memory address, or go into idle. Note that the memory at the destination
address must be initialized with valid code before the bootloader is
executed. Selecting boot mode 000b will disable the PDROM. The MPU
core specifies the boot mode through the DSP_BOOT_CONFIG register.
For more information on the DSP subsystem bootloader and the
DSP_BOOT_CONFIG register, see section 12.4.
SPRU890A