Instruction Cache Operation - Texas Instruments OMAP5910 Reference Manual

Address Type Pseudo Instruction
...
Ext Memory DSP code
Ext Memory GCR = #0xce2f
Ext Memory NWCR = #0x000f
Ext Memory RCR1 = #0x000f
Ext Memory RCR2 = #0x000f
Ext Memory Set CAEN in ST3_55
Ext Memory Poll ENABLE bit of ISR ; Wait until cache is enabled
Ext Memory goto Load_RAM_sets
...
Load_RAM_sets:
Int Memory RTR1 = #0x0800
Int Memory Poll TAG_VALID in RCR1 ; Wait until line is filled in RAM set 1
Int Memory RTR2 = #0x0801
Int Memory Poll TAG_VALID in RCR2 ; Wait until line is filled in RAM set 2
Int Memory goto Back_from_RAM_set_preload
...
Back_from_RAM_set_preload:
Ext Memory DSP code
Ext Memory DSP code
...
4.2.3

Instruction Cache Operation

4.2.3.1 How the I-Cache Uses the DSP core Fetch Address
SPRU890A
; Select 2−way cache and two RAM sets
; Initialize logic for 2−way cache
; Initialize logic for RAM set 1
; Initialize logic for RAM set 2
; Turn on I-Cache
; Update RAM set tag for bank1
; Update RAM set tag for bank2
When the DSP core requests instructions, it requests 32 bits at a time. With
each request, the DSP core sends a fetch address that indicates where to read
the 32 bit requested word. When a fetch request arrives, the I-Cache performs
an instruction presence check; that is, it determines whether the requested
word is available in the 2-way cache and/or any RAM sets included in the
I-Cache configuration.
Because the 2-way cache and RAM-set architectures are different, the
I-Cache interprets the fetch address differently when searching the 2-way
cache and when searching the RAM set. Section 4.2.3.1 explains the
differences.
Section 4.2.3.2 describes the steps of the instruction presence check and
explains the factors that determine whether the I-Cache fetches the requested
word from a RAM set, from the 2-way cache, or from DSP external memory.
Whenever possible, the I-Cache gets the requested word from a RAM set. If
the requested word is in a RAM set but not in the 2-way cache, the word is
fetched from the RAM set and the 2-way cache is not loaded with that word.
Figure 8 and Table 2 describe how the I-Cache uses the fetch address for the
2-way cache. Figure 9 and Table 3 describe the same for a RAM set.
Instruction Cache
DSP Subsystem 35