System Traffic Considerations - Texas Instruments OMAP5910 Reference Manual

Instruction Cache
4.4.3

System Traffic Considerations

4.5 Configuring the I-Cache With the 2-Way Cache and Two RAM Sets
4.5.1 Architectural/Operational Description
46 DSP Subsystem
Note:
The code that loads the RAM sets cannot be read from DSP external
memory at the same time that the RAM sets are being loaded from memory.
Therefore, place the RAM-set load code in memory that is internal to the DSP
subsystem.
All DSP subsystem accesses to DSP external memory eventually go through
the traffic controller. The access time for a DSP external memory request will
depend on the amount of competing accesses in the traffic controller, as well
as the configurations of the OMAP external memory interfaces (EMIFF and
EMIFS).
The instruction cache is used to store recently-used instructions stored in DSP
external memory. The I-Cache automatically fills its two-way cache with
instruction accesses from DSP external memory, thus, subsequent accesses
are essentially fetched from internal memory. Blocks of instructions can also
be pre-fetched into the RAM set blocks.
This section describes how to configure the I-Cache such that the 16KB
two-way cache is enabled with two 4KB RAM set blocks.
When the DSP core fetches an instruction from DSP external memory, the
I-Cache performs an instruction presence check to determine whether the
32-bit requested word is available in the I-Cache. If the instruction is found, the
I-Cache returns the requested instruction to the DSP core, otherwise a DSP
external memory access request is forwarded to the DSP external memory
interface (EMIF). The EMIF passes that request to the DSP Memory
Management Unit (if enabled). After address translation, the DSP MMU places
a request to the traffic controller, which accesses shared memory via the
OMAP external memory interfaces (EMIFF and EMIFS).
SPRU890A