Emif Fast Interface Sdram Mrs Register—Emrs Mode (Emiff_Mrs) - Texas Instruments OMAP5910 Technical Reference Manual

Table 4–21. EMIF Fast Interface SDRAM MRS Register—EMRS Mode (EMIFF_MRS)
Bit Field
31–5 Reserved
4–3 TCSR
2–0 PASR
Notes: 1) Reset value is defined by the default mode of the register (see Table 4–20).
Value Description
Read is undefined. Writes must be zero.
SDRAM EMRS register temperature compensated
self-refresh setting:
00 70 degrees Celsius maximum case temperature
01 45 degrees Celsius maximum case temperature
10 15 degrees Celsius maximum case temperature
11 85 degrees Celsius maximum case temperature
Bit descriptions are given with respect to standard
SDRAM devices and must be verified with the actual
SDRAM chosen for the application.
SDRAM EMRS register partial array self-refresh
coverage setting:
000 All banks
001 Half array
010 Quarter array
011 Reserved
100 Reserved
101 Reserved
110 Reserved
111 Reserved
Bit descriptions are given with respect to standard
SDRAM devices and must be verified with the actual
SDRAM chosen for the application.
Traffic Controller Memory Interface Registers
Memory Interface Traffic Controller
Reset
Access
Value
R
See
Note 1
R/W
See
Note 1
R/W
See
Note 1
4-53