Register Access Ready (Ardy) Set Conditions - Texas Instruments OMAP5910 Technical Reference Manual

Register Access Ready (ARDY)
Table 7–56. Register Access Ready (ARDY) Set Conditions
Mode
Master transmit
Master receive
Master transmit or
receive
Master transmit or
receive
Slave transmit
Slave receive
No Acknowledgment (NACK)
This bit (2) when set to 1 indicates that the previously programmed data and
command (receive or transmit, master or slave) have been performed and the
status bit has been updated. This flag is used by the local host to let it know
2
that the I C registers are ready to be accessed again.
Others
STP = 1, RM = 0
STP = 1, RM = 0
STP = 0, RM = 0
RM=1
–
–
This bit is cleared to 0 by the core with a read of the matching interrupt vector
in I2C_IV register.
-
0: No action
-
1: Access ready
Value after reset is low.
The no acknowledge flag bit (1) is set when the hardware detects no acknowl-
edge has been received.
This bit is cleared to 0 by the core with a read of the matching interrupt vector
in I2C_IV register.
-
0: Normal/no action required
-
1: NACK
Value after reset is low.
When a NACK occurs, the system has to perform the following actions to
recover:
1) Read the INTCODE in the I2C_IV register to release NACK in I2C_STAT.
ARDY Set Conditions
DCOUNT=0
DCOUNT = 0 and receiver FIFO empty
DCOUNT passed 0
Never
Stop condition received from master
Stop condition and receiver FIFO empty
MPU Public Peripherals
Inter-Integrated Circuit Controller
7-73