Mmc System Interrupt Register (Mmc_Ie) - Texas Instruments OMAP5910 Technical Reference Manual

MMC/SD Host Controller
Table 7–102. MMC System Interrupt Register (MMC_IE)
Bit Name
15 Reserved
14 Card_Err_IE
13 Card_IRQ_IE
12 OCR_busy_IE
11 A_Empty_IE
10 A_Full_IE
9 Reserved
8 Cmd_CRC_IE
7 Cmd_timeout_IE
6 Data_CRC_IE
5 Data_timeout_IE
4 EOF_Busy_IE
3 Block_RS_IE
2 Card_Busy_IE
1 Reserved
0 End_of_Cmd_IE
7-142
Description
Card status error interrupt enable
Card IRQ interrupt enable
OCR busy interrupt enable
Buffer almost empty interrupt enable
Buffer almost full interrupt enable
Command CRC error interrupt enable
Command response time-out Interrupt enable
Data CRC error interrupt enable
Data response time-out interrupt enable
Card exit busy state interrupt enable
Block received/sent interrupt enable
Card enter busy state interrupt enable
End of command interrupt enable
Common to all bits:
-
When a bit location is set to 1 by the local host, an interrupt is signaled to
the local host if the corresponding bit location in MMC_STAT register is
asserted to 1 by the core.
-
If set to 0, the interrupt is masked and not signaled to the local host.
J
0: Interrupt disabled
J
1: Interrupt enabled
-
Values after reset are low (all bits).