Sample Rate Generator 1 Configuration (Srgr[1,2]); Sample Rate Generator 2 Configuration (Srgr[1,2]) - Texas Instruments OMAP5910 Technical Reference Manual

McBSP3
9.4.4.5 Sample Rate Generator Configuration (SRGR[1,2])
Table 9–21. Sample Rate Generator 1 Configuration (SRGR[1,2])
(DSP_Write (0x00FF) => SRGR1)
Bit Config Value
15–8 0000 0000b
7–0 1111 1111b
Table 9–22. Sample Rate Generator 2 Configuration (SRGR[1,2])
(DSP_Write (0x2000) => SRGR2)
Bit Config Value
15 0b
14 0b
13 1b
12 0b
11–0 0000 0000
0000b
9.4.4.6 Start Sample Rate Generator (SPCR2)
9-20
DSP_Write (0x00FF) => SRGR1; set up SRGR1 per below configuration.
Description
These bits ignored by the FSGM=0 (SRGR2[12:12])
Set sample rate generator clock divider
DSP_Write (0x2000) => SRGR2; set up SRGR2 per below configuration.
Description
Set sample rate generator clock synchronization
Set clock polarity
Sample rate generator clock derived from DSP clock
Set frame-synchronization
These bit ignored by the FSGM=0 (SRGR2[12:12])
Wait two CLKSRG clock cycles.
DSP_Write SPCR2 or (0x0040) => SPCR2; bring sample rate generator out
of reset.
Note:
Wait two sample rate clock for McBSP stability.