Event Capture Process; Mpu Input/Output Registers - Texas Instruments OMAP5910 Technical Reference Manual

Figure 7–16. Event Capture Process
MPUIO_IN(15:0)
7.3.8 MPU I/O Registers
Table 7–12. MPU Input/Output Registers
Register
INPUT_LATCH
OUTPUT_REG
IO_CNTL
KBR_LATCH
KBC_REG
GPIO_EVENT_MODE_REG
GPIO_INT_EDGE_REG
KBD_INT
GPIO_DEBOUNCING_REG
and GPIO MASKIT
Debouncing
time (steps of
31 µs)
31 µ-8 ms
Clock event and pin select
GPIO_EVENT_MODE_REG
Start address in the MPU I/O range (hex): FFFB:5000
Table 7–12 lists the MPU I/O registers. Table 7–13 through Table 7–25
describe the individual registers.
Description
General-purpose input
Output
Input/Output control
Keyboard row inputs
Keyboard column outputs
GPIO event mode
GPIO interrupt edge
Keyboard interrupt
Interrupt edge
GPIO_INT_EDGE_REG
Transition matches
the programmed
edge and not
masked?
Enable
Latch the
MPUIO_IN(15:0)
status on a clock event
GPIO_LATCH_REG
R/W
R
R/W
R/W
R
R/W
R/W
R/W
R
Interrupt mask
GPIO_MASKIT
If yes, then GPIO
Interrupt
GPIO_INT status
register:
GPIO_INT
Size Address
16 bits FFFB:5000
16 bits FFFB:5000
16 bits FFFB:5000
16 bits FFFB:5000
16 bits FFFB:5000
16 bits FFFB:5000
16 bits FFFB:5000
16 bits FFFB:5000
MPU Public Peripherals
MPU I/O
TIPB
Offset
0x00
0x04
0x08
0x10
0x14
0x18
0x1C
0x20
7-25