Instruction Cache - Texas Instruments OMAP5910 Technical Reference Manual

3.3.2

Instruction Cache

The DSP instruction cache (I-cache) module is a special-purpose, tightly
coupled, RAM-based program memory. The module is designed to
significantly improve the CPU performance by buffering the instructions most
recently fetched from external memory. The entire external program memory
space is cacheable.
The I-cache consists of the following:
1) One 2-way cache. The cache uses two-way set associative mapping and
holds up to 16K bytes: 512 sets, two lines per set, four 32-bit words per
line.
2) Two RAM sets (1 and 2). These two banks of RAM can be used to store
blocks of code. Each RAM set holds up to 4K bytes: 256 lines, four 32-bit
words per line. Before enabling the I-cache, you configure the I-cache to
use zero, one, or both RAM sets
The I-cache can be enabled, disabled, or modified at any time by the program-
mer using software control. The TIPB bridge allows access to the cache con-
figuration registers in the DSP I/O space. At reset the I-cache is disabled. The
user must configure the I-cache to be able to use the ramset.
The initial normal cache hit is a one-wait-state operation. Thereafter, the
I-cache performs a simple branch prediction for cache access (i.e., a branch
not taken is always assumed). With this feature, no-branch continuous fetches
are no-wait-state operations. The instruction cache returns one 32-bit word for
each fetch. Fetches are always aligned on a 32-bit boundary.
When a cache miss occurs, wait states are inserted that are dependent upon
the external memory access time. The I-cache retrieves instructions from ex-
ternal memory in a burst of four 32-bit words (to fill cache line). To reduce the
penalty of misses, a streaming feature is implemented where the instruction
word requested by the DSP is sent back as soon as it is retrieved from external
memory, so all four 32 bit words do not have to be loaded into the cache line
first. Additionally, program fetch requests that fall in a cache line already being
retrieved due to a previous miss are serviced as soon as the word becomes
available. This streaming feature can increase the performance of even non-
looping code executing from external memory.
The instruction cache supports emulation debug read and breakpoint/watch-
point insertion by invalidating cache lines with the corresponding data
changed in the external memory space.
The DSP I-cache on OMAP5910 functions as described in the TMS320C55x
DSP Instruction Cache Reference Guide (literature number SPRU576). See
this document (I-Cache Type A section) for additional details on the DSP
I-cache operation.
DSP Memory
DSP Subsystem 3-11