Configuring The I-Cache With The 2-Way Cache And One Ram Set - Texas Instruments OMAP5910 Reference Manual

4.4

Configuring the I-Cache With the 2-Way Cache and One RAM Set

4.4.1 Architectural/Operational Description
4.4.2 Software Configuration
SPRU890A
The instruction cache is used to store recently-used instructions in the DSP
external memory. The I-Cache automatically fills its two-way cache with
instruction accesses from DSP external memory, thus, subsequent accesses
are essentially fetched from internal memory. Blocks of instructions can also
be pre-fetched into the RAM set blocks.
This section describes how to configure the I-Cache such that the 16KB
two-way cache is enabled with one 4KB RAM set block.
When the DSP core fetches an instruction from DSP external memory, the
I-Cache performs an instruction presence check to determine whether the
32-bit requested word is available in the I-Cache. If the instruction is found, the
I-Cache returns the requested instruction to the DSP core. Otherwise, a DSP
external memory access request is forwarded to the external memory
interface (EMIF). The EMIF passes that request to the DSP Memory
Management Unit (if enabled). After address translation, the DSP MMU places
a request to the traffic controller which accesses shared memory via the
OMAP external memory interfaces (EMIFF and EMIFS).
Follow this procedure to configure with 2-way cache and one RAM set:
1) Write to the appropriate control registers:
Write CE0Fh to GCR to indicate one RAM set.
Write 000Fh to NWCR to initialize the logic for the 2-way cache.
Write 000Fh to RCR1 to initialize the logic for RAM set 1.
2) Set the cache enable bit (CAEN) bit of DSP core status register ST3_55
to send an enable request to the I-Cache.
3) Poll the I-Cache-enabled (ENABLE) bit of ISR until ENABLE = 1. (The
I-Cache is not instantaneously enabled.)
4) Write the desired tag to RTR1. When you write to the tag register, the tag
is used to immediately fill RAM set 1 from DSP external memory.
While the I-Cache is enabled, you can write to the tag register at any time
to change the RAM-set address range. Each time you load the tag register,
RAM set 1 is immediately filled from the selected address range.
5) To monitor the RAM-set filling, poll the tag-valid bit: When TAG_VALID = 1
in RCR1, the I-Cache has finished filling RAM set 1.
Instruction Cache
DSP Subsystem 45