Interrupt Code (Intcode) Conditions - Texas Instruments OMAP5910 Technical Reference Manual

Table 7–58. Interrupt Code (INTCODE) Conditions
2
Table 7–59. I C Buffer Configuration Register (I2C_BUF)
Bit Name
15 RDMA_EN
14–8 –
7 XDMA_EN
6–0 –
Receive DMA Channel Enable (RDMA_EN)
Transmit DMA Channel Enable (XDMA_EN)
Interrupt Code
000
001
010
011
100
101
Others
2
The read/write I C buffer configuration register (I2C_BUF) enables DMA
transfers.
Description
Receive DMA channel enable
Reserved
Transmit DMA channel enable
Reserved
When this bit (15) is set to 1, the receive DMA channel is enabled and the
receive data ready interrupt is automatically disabled (RRDY_IE bit cleared).
-
0: Receive DMA channel disabled
-
1: Receive DMA channel enabled
Value after reset is low.
When this bit is set to 1, the transmit DMA channel is enabled and the transmit
data ready interrupt is automatically disabled (XRDY_IE bit cleared).
-
0: Transmit DMA channel disabled
-
1: Transmit DMA channel enabled
Value after reset is low.
2
The read/write I C data counter register (I2C_CNT) controls the numbers of
2
bytes in the I C data payload.
Interrupt Occurred
None
Arbitration lost interrupt
No acknowledgement interrupt/general call
Register access ready interrupt
Receive data ready interrupt
Transmit data ready interrupt
Reserved
MPU Public Peripherals
Inter-Integrated Circuit Controller
Priority
–
Highest
↓
Lowest
–
7-75