Transmit Dma Transfers - Texas Instruments OMAP5910 Technical Reference Manual

Multichannel Serial Interfaces
9.5.1.5 DMA Channel Operation

Transmit DMA Transfers

Figure 9–14. Transmit DMA Transfers
TI peripheral bus
dma add
Ad0 Ad1
Val0 dum
9-36
Then, to release the interrupt signal and reset the corresponding status bits:
-
DSP_WRITE(1) =
J
STATUS_REG(1) for FERR_INT release
J
STATUS_REG(2) for RX_INT release
J
STATUS_REG(4) for TX_INT release
Both transmit and receive operations can be supported by DMA. DMA support
is enabled by control bits in the MAIN_PARAMETERS_REG:
-
MAIN_PARAMETERS_REG(15:14) = DMA_ENABLE(1:0)
J
TX_DMA_REQ enabled when DMA_ENABLE(0) = 1
J
TX_DMA_REQ disabled when DMA_ENABLE(0) = 0
J
RX_DMA_REQ enabled when DMA_ENABLE(1) = 1
J
RX_DMA_REQ disabled when DMA_ENABLE(1) = 0
A new transmit DMA transfer is initiated during the transmission of the last
channel of a frame, at which time all data in the transmit registers (TX_REGs)
has been moved to shift registers; the TX_REGs are now ready to be rewritten.
If N channels are used, the DMA controller successively accesses all consecu-
tive registers between TX_REG(0) and TX_REG(N-1). If some channels
between TX_REG(0) and TX_REG(N-1) are not used, the DMA controller
writes dummy values when addressing these unused registers (see
Figure 9–14).
ad
Adn
n-1
dum Valn
MCSI
MCSI Tx MCSI Tx
registers shift
registers
Value 0 Value 0
Dummy 1 Empty 1
Dummy n-1 Empty n-1
Value n Value n
Empty n+1 Empty n+1
Empty N Empty N
Serial output
Value 0 Value n