Tipb (Public) Bridge Registers; Tipb Control Register (Tipb_Cntl) - Offset: X00; Tipb Bus Allocation Register (Tipb_Bus_Alloc) - Offset: X04 - Texas Instruments OMAP5910 Technical Reference Manual

MPU TI Peripheral Bus Bridges
Table 2–60. TIPB (Public) Bridge Registers
Register Name
TIPB_CNTL
TIPB _BUS_ALLOC
MPU_TIPB_CNTL
ENHANCED_TIPB_CNTL
ADDRESS_DBG
DATA_DEBUG_LOW
DATA_DEBUG_HIGH
DEBUG_CNTR_SIG
Table 2–61. TIPB Control Register (TIPB_CNTL) – Offset: x00
Bit Description
15–8 TIPB bus access time out
7–4 Division factor of nASTROBE[1]
3–0 Division factor of nASTROBE[0]
Table 2–62. TIPB Bus Allocation Register (TIPB_BUS_ALLOC) – Offset: x04
Bit Value Description
5–4 Reserved.
The reset value of these bits does not have to be
changed for this register to operate correctly.
3 MPU has higher priority than DMA transfers regarding
TIPB allocation when it is in exception mode.
2–0 Defines TIPB priority between MPU and DMA
0 MPU has priority over DMA.
1 DMA has priority over MPU.
2-68
Descriptions
TIPB control
TIPB bus allocation
MPU TIPB control
Enhanced TIPB control
Debug address
Debug data LSB
Debug data MSB
Debug control signals
R/W Size Address
R/W 16 bits FFFE:D300
R/W 16 bits FFFE:D304
R/W 16 bits FFFE:D308
R/W 16 bits FFFE:D30C
R 16 bits FFFE:D310
R 16 bits FFFE:D314
R 16 bits FFFE:D318
R 8 bits FFFE:D31C
Size Access
8 R/W
4 R/W
4 R/W
Size Access
2 R/W
1 R/W
3 R/W
Reset
Value
0xFF11
0x0009
0x0000
0xFFFF
0xFFFF
0xFFFF
0xFFFF
0xF8
Reset
Value
0xFF
0x1
0x1
Reset
Value
00
1
0x1