Pin Control Register Configuration (Dsp_Write(0X0A0B) => Pcr) - Texas Instruments OMAP5910 Technical Reference Manual

9.4.4.14 Pin Control Register Configuration
Table 9–24. Pin Control Register Configuration (DSP_Write(0x0a0b) => PCR)
Bit Config Value
15–14 00b
13 0b
12 0b
11 1b
10 0b
9 1b
8 0b
7 0b
6 0b
5 0b
4 0b
3 1b
2 0b
1 1b
0 1b
DSP_Write(0x0000) => SPCR2; set up SPCR2 as initial configuration.
Note:
This setup is not needed after reset.
DSP_Write(0x0a0b) => PCR; set up PCR per below configuration.
Description
Reserved
Set serial port mode for DX, FSX and CLKX pins
Set serial port mode for DR, FSR and CLKR pins
TX frame-synchronization signal driven by internal generator
RX frame-synchronization signal derived by external source
McBSP is set master and generate clock by internal source
CLKR set input pin and derived by external source
Sample rate generator input clock mode bit
CLKS pin status (no meaning in OMAP5910)
DX pin status
DR pin status
Set FSX polarity as active high
Set FSR polarity as active high
Set CLKX polarity as data driven on falling edge
Set CLKR polarity as data sampled on rising edge
DSP Public Peripherals
McBSP3
9-23