Mpu Tipb Control Register (Mpu_Tipb_Cntl_Reg) - Offset: X08; Enhanced Tipb Control Register (Enhanced_Tipb_Cntl) - Offset: X0C; Address Debug Register (Address_Dbg) - Offset: X10; Data Debug Register Lsb (Data_Debug_Low) - Offset: X14 - Texas Instruments OMAP5910 Technical Reference Manual

Table 2–63. MPU TIPB Control Register (MPU_TIPB_CNTL_REG) – Offset: x08
Bit Value Description
1 1 Write buffer is enabled for strobe domain 1.
0 Write buffer is bypassed.
0 1 Write buffer is enabled for strobe domain 0.
0 Write buffer is bypassed.
Table 2–64. Enhanced TIPB Control Register (ENHANCED_TIPB_CNTL) – Offset: x0C
Bit Description
3 When low, a tc_abort interrupt is sent back to the MPU, when
MPU TIPB access is timed out.
2 When high, incoming signals from MPU and DMA are clocked.
Used when running at high frequency.
1 When low, an interrupt is sent to the MPU when a TIPB write
access is aborted or when any TIPB access has a size mismatch.
When high, the interrupt is masked.
0 A value of 1 enables the time-out feature.
Table 2–65. Address Debug Register (ADDRESS_DBG) – Offset: x10
Bit Description
15–0 Address from MPU memory interface saved on abort or ac-
cess size mismatch
Table 2–66. Data Debug Register LSB (DATA_DEBUG_LOW) – Offset: x14
Bit Description
15–0 Bytes 15–0 of data bus from MPU
MPU TI Peripheral Bus Bridges
Size Access
1 R/W
1 R/W
Size Access
1 R/W
1 R/W
1 R/W
1 R/W
Size Access
16 R 0xFFFF
Size Access
16 R
MPU Subsystem
Reset
Value
0
0
Reset
Value
1
1
1
1
Reset
Value
Reset
Value
0xFFF
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