Cp15 Id Register; Cp15 Cache Information Register (Cir); Field - Texas Instruments OMAP5910 Technical Reference Manual

Coprocessor 15
Table 2–4. Reading From CP15 Register 0
Function Opcode_2
†
Read ID 0bXXX
Read CIR 0b001
† All opcodes [opcode_2,CRm] except [1,0] return the TI925T ID.
Table 2–5. CP15 ID Register
Bit Name
31–24 Implementers
23–16 Architecture version
15–4 Part number
3–0 Reserved
Table 2–6. CP15 Cache Information Register (CIR)
Bit Name
31–29 Reserved
28–25 Cache type
24 ID
23–21 Reserved
20–18 D-cache information
17–15 D-cache information
2-12
CRm
0bXXXX
0b0000
Function
Contains the ASCII code of the implementer trademark (0x54 = Texas
Instruments)
Contains the architecture version (0x02 Version v4T)
Contains a 3-digit part number in binary-coded decimal format.The OS bit
O in the TI925T configuration register sets the value of these fields as
follows:
915 in TI925T mode
925 in Windows CE mode
Contains the microprocessor revision number 2
Value Function
0 Read as 0.
Cache type: read as 0010. The cache provides clean-cache
entry and flush-cache-entry with a cache index in addition of the
operations with virtual address (also called clean-cache-step or
flush-cache-step). The format of the clean-cache-entry is given
in the Register 7: Cache Operations section.
0 Unified I-/D-cache
1 Harvard cache
0 Read as 0.
Base value of D-cache size (same format as for I-cache)
Base value of D-cache associativity (same format as for I-cache)
Rd Instruction
TI925T ID MRC p15, 0, Rd, c0, c0, 0
Cache info MRC p15, 0, Rd, c0, c0, 1