Dma Lcd Control Register (Dma_Lcd_Ctrl) - Texas Instruments OMAP5910 Technical Reference Manual

Registers
Table 5–25. DMA LCD Control Register (DMA_LCD_CTRL)
Bit Name
15–7 RESERVED
6 LCD_SOURCE
5 BUS_ERROR_
IT_COND
4 FRAME_2_
IT_COND
3 FRAME_1_
IT_COND
2 BUS_ERROR_
IT_IE
1 FRAME_IT_IE
5-54
Value Description
Memory source for the LCD channel
This bit indicates the memory source for the next LCD
transfer.
0 Memory source is EMIFF.
1 Memory source is IMIF.
Status LCD channel register (must be reset after
read)
0 No bus error interrupt detected
1 Bus error interrupt detected
Status LCD channel register (must be reset after
read)
0 No end of frame 2 interrupt detected
1 End of frame 2 interrupt detected
Status LCD channel register (must be reset after
read)
0 No end of frame 1 interrupt detected
1 End of frame 1 interrupt detected
Bus error interrupt enable
0 Interrupt disabled
1 Interrupt enabled
End frame interrupt enable
0 Interrupt disabled
1 Interrupt enabled
Reset
Type
Value
RW 0
R–R 0
R–R 0
R–R 0
RW 0
RW 0