Spi Master Configuration Bits - Texas Instruments OMAP5910 Technical Reference Manual

Figure 7–52. SPI Master Configuration Bits
Table 7–112. MMC SDIO Mode Configuration Register (MMC_SDIO)
Bit Name
15–14 Reserved
13 CER1_3_En
12–6 Reserved
5 DTO_PS_En
4–0 Reserved
Card Status Error on Bit 3 of Response R1 Enable (CER1_3_En)
SPI MASTER Configuration
POL PHA
0 0
0 1
1 0
1 1
This register provides additional controls for the MMC/SD interface. It is also
reserved for future SDIO operation (not supported in present version).
Description
Card status error on bit 3 of response 1 enable
Data time-out prescaler enable
This bit (13) must be set to 1 for SD cards only or application-specific com-
mands that generates an error.
If set to 1, a card status error is generated if bit 3 of the status is 1 for a R1 or
R1b response.
-
0: Error on bit 3 masked
-
1: Card status errors on bit 3 of response 1 enabled (SD card or application
specific only)
Value after reset is low.
SPI Mode
0
SPI_CLK
1
SPI_CLK
2
SPI_CLK
3
SPI_CLK
MPU Public Peripherals
MMC/SD Host Controller
7-155