Dsp Core Bits For Controlling The I-Cache; Flow Chart Of The Line Load Process - Texas Instruments OMAP5910 Reference Manual

Figure 10.

Flow Chart of the Line Load Process

4.2.4

DSP Core Bits for Controlling the I-Cache

SPRU890A
I-Cache must load
2-way cache line
or RAM set line
Command EMIF to read
four 32-bit words from
DSP external memory
Is
word
received
?
Yes
Write word to line
Is
it the
requested
word
?
Yes
Deliver word to
I unit of DSP core
The I-Cache is controlled not only through the I-Cache registers but also
through three bits located in status register ST3_55 of the DSP core. These
bits are highlighted in Figure 11. For more details about ST3_55, see the
TMS320C55x DSP CPU Reference Guide (SPRU371).
No
No
Line
load done
?
Yes
End
Instruction Cache
Wait for
next word
No
DSP Subsystem 39