Mmu Tlb Global Flush Register (Gflush_Reg) - Texas Instruments OMAP5910 Reference Manual

Table 36. MMU LSB RAM Entry Register (RAM_L_REG) Field Descriptions
(Continued)
Bits Field
9−8 AP
7−0 Reserved
6.5.13

MMU TLB Global Flush Register (GFLUSH_REG)

Figure 59. MMU TLB Global Flush Register (GFLUSH_REG)
31
Note: R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Table 37. MMU TLB Global Flush Register (GFLUSH_REG) Field Descriptions
Bits Field
31−1 Reserved
0 GLOBAL_FLUSH
SPRU890A
Value Description
Access permission bits. These bits determine the access permission
for the physical memory covered by the TLB entry.
00 or No access.
01
10 Read-only access.
11 Full access.
These bits are not used.
The Global Flush Register flushes all TLB entries that are not preserved. When
the GLOBAL_FLUSH bit is set, the VALID bit of all entries with
PRESERVED = 0 is cleared.
Note:
A global flush does not change the first-level table base address or the victim
pointer and base pointer.
Reserved
R-0
Value Description
These bits are not used.
TLB global flush. Setting this bit flushes all TLB entries that are not
preserved. After the flush operation has completed, this bit is
automatically cleared.
0 TLB global flush completed.
1 Flush the TLB.
DSP Memory Management Unit
1
GLOBAL_
FLUSH
RW-0
DSP Subsystem
0
115