Watchdog Timer Interrupt - Texas Instruments OMAP5910 Technical Reference Manual

Watchdog Timer
8.3 Watchdog Timer
Table 8–13. Watchdog Timer Interrupt
8-10
When powered up, the timer defaults to the watchdog timer for the DSP. This
configuration requires that the user program or the OS periodically write to the
count register before the counter underflows to prevent the timer from generat-
ing a reset to the DSP. This function detects user programs stuck in infinite
loops, which can result in program control loss or runaway programs.
Timer Corresponding Level 1 Interrupt
WD INT13
Note:
By default, this timer is configured as a watchdog timer and, unless disabled
or updated properly, generates a reset of the DSP approximately every
19 seconds. If, during system development, you encounter an unexpected
reset every 19 seconds or so, this is probably the reason.
Be certain to disable the watchdog timer before placing the DSP
processor in deep sleep mode. It must not be left configured as a
watchdog timer.
The watchdog timer underflow resets the DSP. If the input clock is 12 MHz and
the watchdog timer values are left at their power-up state (the value loaded into
the load timer register (LOAD_TIM) is set to the maximum value of 0xFFFF),
reset occurs in approximately 19 seconds.
The watchdog timer uses the clock derived from the clock frequency genera-
tion module for synchronization. This clock is [input clock]/14. When config-
ured as a watchdog timer, the prescaler field (PTV) of the control timer register
(CNTL_TIMER) is fixed to 7. When configured as a general-purpose timer, the
prescaler field can range from 0 to 7. The time from writing a new value to
counter underflow is:
between 256*t to 16,777,216*t
clk
where t = [input clock]/14 for a clock frequency of 12 MHz
clk
and the reset time is: 298 µs < t > 19 s).
clk