Emif Fast Interface Sdram Mrs Register—Default (Emiff_Mrs) - Texas Instruments OMAP5910 Technical Reference Manual

Traffic Controller Memory Interface Registers
Table 4–20. EMIF Fast Interface SDRAM MRS Register—Default (EMIFF_MRS)
Bit Field
31–10 Reserved
9 WBST
8–7 Reserved
6–4 CASL
3 S/I
2–0 PGBL
Note: When the CONF_MOD_EMRS_CTRL bit field (bit 13) of the OMAP5910 control register (MOD_CONF_CTRL_0) is
set, the device reconfigures bank settings to write out the EMIFF_MRS register as EMRS commands (see
Table 4–21).
4-52
Value Description
Read is undefined. Writes must be zero.
Write burst must be 0 (burst write same as burst
read).
Read is undefined. Writes must be zero.
CAS latency:
001 CAS latency = 1
010 CAS latency = 2
011 CAS latency = 3 (default at reset)
Serial = 0. This bit must be 0.
Interleave = 1. Reserved. Do not use this setting.
Specifies page burst length to be programmed into
SDRAM MRS configuration register. The length must
always be programmed as full-page burst length
(111). (This length is not necessarily the burst length
at which the EMIFF operates, but rather a setting for
the SDRAM MRS register.)
Reset
Access
Value
R All 0
R/W 0
R/W 00
R/W 011
R/W 0
R/W 111