Behavior Of A X25C02 Eeprom Read Cycle; Behavior Of A Xl93Lc66 Eeprom Read Cycle - Texas Instruments OMAP5910 Reference Manual

MicroWire Interface
Figure 2.

Behavior of a X25C02 EEPROM Read Cycle

WIRE_NCS
UWIRE.SCLK
UWIRE.SDO 0
UWIRE.SDI
Figure 3.

Behavior of a XL93LC66 EEPROM Read Cycle

WIRE_NCS
UWIRE_SCLK
UWIRESDO
UWIRE_SDI
18
MicroWire Interface
After the loading of the transmit data register (TDR), a write process is
activated by setting the START bit to 1 and by writing a value different from zero
to the NB_BITS_WR field.
A read process is always simultaneous with a write process, which means that
at every serial clock, SCLK, cycle data is read. After having finished a write
process (if necessary), a number (defined by the NB_BITS_RD) of SCLK
cycles is generated to allow the storage of data from the serial input DI.
The transmitted data word is shifted out on the rising or falling edge of the serial
clock (according to the value of the CSx_EDGE_WR bits of the setup
registers). The received data word is shifted in on the falling or rising edge of
the serial clock (according to the value of the CSx_EDGE_RD bits of the setup
registers). When the CSx_EDGE_WR and CSx_EDGE_RD bits have the
same value, it is assumed that the device behavior is the one shown in
Figure 2. Otherwise, the required behavior of the external device is shown in
Figure 3.
0 0 0 0 0 1 1 A7
On the DO line, data is generated from the MicroWire interface on the SLCK
falling edge and read by the EEPROM interface on the SCLK rising edge.
On the DI line, data is generated from the EEPROM interface on the SCLK
falling edge and read by the MicroWire interface on the SCLK falling edge.
1 1 0 A7 A6 A5 A4 A3 A2 A1 A0
On the DO line, data is generated from the MicroWire interface on the SLCK
falling edge and read by the EEPROM interface on the SCLK rising edge.
A6 A5 A4 A3 A2 A1 A0
D15 D14 D13
D7 D6 D5 D4 D1 D0
D1 D0
SPRU686