Dma Channel Source Start Address-Lower Bits Register (Dma_Cssa_L) - Texas Instruments OMAP5910 Technical Reference Manual

Table 5–16. DMA Channel Source Start Address–Lower Bits Register (DMA_CSSA_L)
Bit Name
15–0 Source start
address, lower
bits
Table 5–17. DMA Channel Source Start Address–Upper Bits Register (DMA_CSSA_U)
Bit Name
15–0 Source start
address, upper
bits
Table 5–18. DMA Channel Destination Start Address–Lower Bits Register (DMA_CDSA_L)
Bit Name
15–0 Destination
start address,
lower bits
This register is written by the DMA to reflect the channel status. It can be read
by the processor (by polling or after an interrupt) to see the channel status. Af-
ter a functional read, all the DMA_CSR bits are automatically cleared. The
DMA_CSR bit is not cleared after an emulation read via the debugger. The reg-
ister bit is only set when its associated DMA_CICR is enabled.
The DMA interrupt status bits are set by hardware and cleared by a software
read operation to DMA_CSR. A subsequent DMA interrupt cannot be issued
until a program read of DMA_CSR has cleared the interrupt status bits. For on-
going operation of the DMA channel, the ISR must read DMA_CSR after each
DMA interrupt.
Description
Lower bits of the source start address, expressed in
bytes. The source start address output by the DMA is an
up-to-32-bit byte address made of the concatenation of
DMA_CSSA_U and DMA_CSSA_L.
Description
Upper bits of the source start address, expressed in
bytes. The source start address output by the DMA is a
32-bit byte address made of the concatenation of
DMA_CSSA_U and DMA_CSSA_L.
Description
Lower bits for the destination start address, expressed in
bytes. The destination start address is up to an up-to-
32-bit byte address made of the concatenation of
DMA_CDSA_U and DMA_CDSA_L.
Type
RW
Type
RW
Type
RW
System DMA Controller
Registers
Reset
Value
Undefined
Reset
Value
Undefined
Reset
Value
Undefined
5-51