Real-Time Clock
Figure 7–64. Positive and Negative Compensation Effect
32-kHz clock
Timer counter
7FFA
Second update
32-kHz clock
Timer counter
7FFA
Second update
32-kHz clock
Timer counter
7FFA
Second update
7-176
Figure 7–64 summarizes positive and negative compensation effect.
7FFB
7FFC
Negative compensation: comp_reg = +2
7FFB
7FFC
Positive compensation: comp_reg = –2 (0xFFFE)
7FFB
7FFC
No compensation
7FFD
7FFE
7FFF
7FFD
7FFE
7FFF
7FFD
7FFE
7FFF
0000
0001
0002
0003
Two cycles are
removed from next
second.
7FFE
7FFF
Two cycles are added
to current second.
0000