Dsp Subsystem Clocking And Reset Control - Texas Instruments OMAP5910 Technical Reference Manual

DSP Subsystem Clocking and Reset Control

3.9 DSP Subsystem Clocking and Reset Control
3-38
The clock generator and system reset module (CLK and RST) manages
operations such as the reset sequences, the clock generation function, the
power-saving modes, idle controls, and setup for the OMAP5910. The clock
domains in the OMAP5910 platform are synthesized by the DPLL1. The DPLL
input clock source is externally supplied from the CLKIN pin.
The MPU manages the master clock configuration for the OMAP5910 device.
The DSP subsystem master clock DSP_CK is enabled at reset until the DSP
is enabled. The EN_DSPCK bit in the clock control register ARM_CKCTL
allows turning off the DSP_CK while the DSP is still in a reset state.
The CLKM2 module generates the individual clock domains for the DSP
subsystem. These clock signals have programmable frequencies based on
divisors of several possible input clock sources. See Chapter 15, Clock Gener-
ation and System Reset Management, for details on the clock generator
peripheral. CLKM2 is considered an MPU private peripheral, except for config-
uration of subdomain clocks for the DSP subsystem discussed in Section
15.2.5.