Reset Considerations - Texas Instruments OMAP5910 Reference Manual

DSP Memory Management Unit
6.2.8

Reset Considerations

6.2.8.1 Software Reset Considerations
6.2.8.2 Hardware Reset Considerations
94 DSP Subsystem
Note:
The DSP EMIF will be stalled, thus stalling the original requestor (either the
DSP core or DMA), while the error is cleared by the MPU core.
The ISR can service each error as follows:
For a pre-fetch or translation fault, the ISR must write a valid entry to the
-
TLB and acknowledge the interrupt through the interrupt acknowledge
register (IT_ACK_REG). The translation table(s) can also be updated
such that the error is not generated again if the TLB entry is evicted or
flushed.
For a TLB miss, the ISR must write a valid entry to the TLB and
-
acknowledge the interrupt through the interrupt acknowledge register
(IT_ACK_REG).
For a permission fault, the MPU core must write a valid entry to the TLB
-
to allow for the requested access type and then acknowledge the interrupt
through the interrupt acknowledge register (IT_ACK_REG). The
translation table(s) can also be updated such that the error is not
generated again if the TLB entry is evicted or flushed.
The ISR may also reset the DSP subsystem in response to any MMU interrupt.
A software reset of the DSP MMU can be initiated by setting the MMU_RESET
bit in the CNTL_REG register of the MMU. After a software reset, the
preserved and valid bits of all the entries in the TLB are cleared. The victim and
base pointers are not affected by a software reset. Also, the table walking logic
does not become disabled after a software reset.
After a hardware reset (section 12.1), the MMU is disabled and the DSP
external memory space is mapped to the first 16M bytes of system memory.
Also, the MMU does not perform any permission checks on DSP external
memory accesses. All MMU registers return to their default state as indicated
in section 6.5.
SPRU890A