I2C System Overview; Inter-Integrated Circuit Controller - Texas Instruments OMAP5910 Technical Reference Manual

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7.8 Inter-Integrated Circuit Controller

2
7.8.1
I
C Protocol Description
2
Figure 7–23. I
C System Overview
Interrupt
handler
Local host
(MPU)
System
DMA
7.8.1.1
Functional Overview
This section describes the I
overview. References to a local host in this section refer to the MPU processor.
I2C_IRQ
I 2 C
controller
I 2 C I/F
pads
I 2 C.SCL
I 2 C.SDA
2
The I
C bus is a multimaster bus. The I
multimaster mode, to which more than one device capable of controlling the
bus can be connected. Including the OMAP5910, each I
nized by a unique address and can operate as either transmitter or receiver
depending on the function of the device. In addition to being a transmitter
or receiver, a device connected to the I
ter or slave when performing data transfers. A master device is the device
which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. During this transfer, any device addressed by this
master is considered a slave.
Inter-Integrated Circuit Controller
2
C protocol. Figure 7–23 shows the I
V DD
Pullup
resisters
I 2 C
R P
R P
compatible
device
SCL
SDA
I 2 C
compatible
device
2
C controller function does support the
2
C bus can also be considered as mas-
MPU Public Peripherals
2
C system
I 2 C
compatible
device
I 2 C
I 2 C
compatible
compatible
device
device
2
C device is recog-
7-57

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