Watchdog Timer Registers - Texas Instruments OMAP5910 Technical Reference Manual

8.3.3

Watchdog Timer Registers

Table 8–16. DSP Watchdog Timer Registers
Register Name
CNTL_TIMER
LOAD_TIM
READ_TIM
TIMER_MODE
Table 8–17. Control Timer Register (CNTL_TIMER)
Bit Name
15–12 Reserved
11–9 PTV
8 AR
7 ST
6–2
1 FREE
0
Table 8–16 shows the DSP watchdog timer registers. Table 8–17 through
Table 8–20 describe the register bits.
Description
Control timer
Load timer
Read timer
Timer mode
Value Description
Prescale clock timer value
0 One-shot timer
1 Autoreload timer
If one-shot mode is selected (AR = 0), this bit is automatically
reset by internal logic when timer is equal to 0.
0 Stop timer
1 Start timer
Reserved
0 Enables emulation suspend function; timer can be frozen during
emulation halt on the DSP.
1 Timer runs free, regardless of emulation halt condition.
Reserved
R/W Size (Bits)
R/W 16
W 16
R 16
R/W 16
DSP Private Peripherals
Watchdog Timer
Reset
Address
Value
x003400 0x0002
x003402 0xFFFF
x003402 0xFFFF
x003404 0x8000
Reset
Value
0
0
0
1
8-13