Dsp Interrupt Interface - Texas Instruments OMAP5910 Technical Reference Manual

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DSP Interrupt Interface

8.5 DSP Interrupt Interface

Functional Description

Edge-Triggered Interrupts

The DSP interrupt interface (DSP_INT_IF) augments the capability of the

DSP interrupt processing by providing user-definable edge-triggered and

level-sensitive implementations for each of the interrupt lines. This is neces-

sary to allow edge-triggered interrupts, since the DSP level 1 interrupts must

be active for greater than two DSP_CLK cycles to be recognized as being

active. The DSP_INT_IF module is clocked by the DSP_INTH_CK clock,

which which is fixed at half the CK_GEN2 frequency (see Chapter 15).

The implementation of each of the interrupt channels to the DSP interrupt

handler is shown in Figure 8–5.

Each interrupt channel processes the incoming interrupt as both an edge-

triggered interrupt and a level-sensitive interrupt. The decision of which

process to use is made by the interrupt (N) edge-triggered enable input, which

of the edge-enable control register. If this bit is 1, the edge-triggered

process path is chosen. If 0, the level-sensitive process path is chosen.

The edge-triggered interrupt process consists of an edge-registration flip-flop

and a chain of four positive-edge triggered timing flip-flops. A negative transi-

tion (falling edge) on the incoming nXIRQ(N) interrupt line sets the edge-regis-

tration flip-flop to 1, and the output of this flip-flop is the edge-triggered inter-

rupt. In addition to activating the output interrupt line nIRQ(N), this output also

propagates through the four timing flip-flops. When the 1 output of the edge-

registration flip-flop has propagated to the fourth flip-flop, an asynchronous

reset is generated, clearing the edge-registration flip-flop and deactivating

nIRQ(N) then lasts between three and four DSP_INTH_CK clock periods,

depending on when the asynchronous falling edge of nXIRQ(N) occurs with

respect to the rising edge of DSP_INTH_CK clock. In OMAP, the frequency of

DSP_INTH_CK clock is set to half the DSP_CLK frequency. The DSP requires

the nIRQ(N) to transition from high to low and to be low for at least two

DSP_CLK cycles, so that nIRQ(N) can be recognized. Also the DSP requires

between two back-to-back interrupts on nIRQ(N), nIRQ(N) be high for at least

one DSP_CLK cycle. nIRQ(N) is generated by the rising edge of

DSP_INTH_CK clock and lasts for a minimum of three DSP_INTH_CK clock

periods (which is actually six DSP_CLK cycles). The requirements on nIRQ(N)

are clearly met.