Dma Channel Control Register (Dmaccr) Field Descriptions - Texas Instruments OMAP5910 Reference Manual

DSP DMA
Table 44. DMA Channel Control Register (DMACCR) Field Descriptions
Bits Field
15−12 Reserved
11 ENDPROG
10 Reserved
128 DSP Subsystem
Value Description
Reserved
End-of-programming bit. Each DMA channel has two sets of
registers: configuration registers and working registers. When
block transfers occur repeatedly because of auto-initialization
(AUTOINIT = 1), you can change the context for the next DMA
transfer by writing to the configuration registers during the current
block transfer. At the end of the current transfer, the contents of the
configuration registers are copied into the working registers, and
the DMA controller begins the next transfer using the new context.
For proper auto-initialization, the DSP core must finish
programming the configuration registers before the DMA controller
copies their contents.
The DMA controller automatically clears the ENDPROG bit after
copying the configuration registers to the working registers. The
DSP core can then program the DMA channel context for the next
iteration of the transfer by programming the configuration registers.
To ensure that auto-initialization waits for the DSP core, follow this
procedure:
1) Make auto-initialization wait for ENDPROG = 1 by clearing
the REPEAT bit (REPEAT = 0)
2) Poll for ENDPROG = 0, which indicates that the DMA
controller has finished copying the previous context. The
configuration registers can now be programmed for the next
iteration.
3) Program the configuration registers.
4) Set ENDPROG (ENDPROG = 1) to indicate the end of
register programming.
0 Configuration registers ready for programming/Programming in
progress.
1 End of programming.
Reserved.
SPRU890A