Mpu Memory Management Unit - Texas Instruments OMAP5910 Technical Reference Manual

MPU Memory Management Unit

2.7 MPU Memory Management Unit
2.7.1 Translation Look-Aside Buffer
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The MPU MMU performs virtual-to-physical address translations and access
permission checks for access to the system memory, and it provides the flexi-
bility and security required for the OS to manage physical memory space
shared by the DSP subsystem and the MPU subsystem. The MPU MMU
provides no protection from DSP shared memory accesses.
The MMU hardware required to perform these functions consists of:
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A 64-entry translation look-aside buffer for instructions (I_TLB)
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A 64-entry translation look-aside buffer for data (D_TLB)
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Access control logic
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Translation table walking logic
The MMU supports memory accesses based on sections or pages:
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Sections represent memory blocks of 1M byte.
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Three different page sizes are supported:
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Large pages consist of 64K-byte blocks of memory.
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Small pages consist of 4K-byte blocks of memory.
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Tiny pages consist of 1K-byte blocks of memory.
Sections and large pages are supported to allow mapping of large regions of
memory while using only a single entry in the TLB.
The TLB contains entries for virtual-to-physical address translation and ac-
cess permission checking. If the TLB contains a translated entry for the virtual
address, the access control logic determines whether the access is permitted.
If access is permitted, the MMU generates the appropriate physical address
corresponding to the virtual address. If access is not permitted, the MMU
sends an abort signal to TI925T.
Upon a TLB miss (that is, the TLB does not contain an entry corresponding to
the virtual address requested), the translation table walking hardware re-
trieves the translation and access permission information from the translation
table in physical memory. Once retrieved, the page or section descriptor is
stored into the TLB at a random location.
Note:
Because the load and store multiple instructions can cross a page boundary,
the permission access is checked for each sequential address.