Mpu Memory Map - Texas Instruments OMAP5910 Reference Manual

Memory Map
Table 3.

MPU Memory Map

Device Name
External Slow Memory Interface (Flash)
FLASH CS0
Reserved
FLASH CS1
Reserved
FLASH CS2
Reserved
FLASH CS3
Reserved
External Fast Memory Interface (SDRAM)
SDRAM
Reserved
Internal Memory Interface (SRAM)
Internal RAM
Reserved
†
Each register must always be accessed using the appropriate data access width as indicated in this table. Failure to do so
may result in unexpected behavior including a TIPB bus error condition with an associated interrupt. Reserved address loca-
tions should never be accessed.
16 Memory Interface Traffic Controller
Table 2. Device Types Associated With Chip-Select (Continued)
CS Device
†
None External synchronous dynamic RAM
†
None Internal SRAM
†
The interface to these memory devices is activated via internal address decoding. There is no
external chip select.
The OMAP5910 peripherals are mapped on the MPU memory space in two
different segments: through STROBE0 (public peripherals) and STROBE1
(private peripherals). Each peripheral has a range of 2K bytes.
Table 3 shows the MPU memory map.
Start Address
System Memory Address Space
0000:0000
0200:0000
0400:0000
0600:0000
0800:0000
0A00:0000
0C00:0000
0E00:0000
1000:0000
1400:0000
2000:0000
2003:0000
End Address Size in Bytes
01FF:FFFF 32M bytes
03FF:FFFF
05FF:FFFF 32M bytes
07FF:FFFF
09FF:FFFF 32M bytes
0BFF:FFFF
0DFF:FFFF 32M bytes
0FFF:FFFF
13FF:FFFF 64M bytes
1FFF:FFFF
2002:FFFF 192K bytes
2FFF:FFFF
†
Data Access
8/16/32 R/W
8/16/32 R/W
8/16/32 R/W
8/16/32 R/W
8/16 R/W
8/16/32 R/W
SPRU673