Clock Control - Texas Instruments OMAP5910 Technical Reference Manual

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Clock Divider (Clk_div)

Figure 7–49. Clock Control

protocol select

1) During the identification phase, the maximal frequency on the MMC CLK line is 400 kHz (reference: bus timing speci-

fications Chapter 6 of the MultiMediaCard System Specification Version 3.1 – June, 2001. MMCA Technical Com-

mittee or the SD Memory Card Specifications – Part 1 Physical Layer Specification, Version 1.0 – March 2000 +

Supplementary Notes Part 1 June 2000. SD Group). That is, you must set a value of 120 into the frequency ratio

2) During data transfer phase the maximum frequency is 16 MHz for MMC cards, 24 MHz for SD cards, and 12 MHz

for SPI serial flash cards.

3) The duty cycles of the generated MMC_CLK and SPI_CLK clock signals depend on the Clk_div value and on the

polarity setting (MMC_SPI:POL) for SPI_CLK signal only. The low- and high-time approximate values can be

computed using set-in rules.

These bits (7-0) define the ratio between a reference clock frequency (48 MHz)

and the output clock frequency on the CLK pin of either the memory card (MMC

or SD) or other 8-bit mode SPI controlled device.

The division factor is exactly the binary encoded decimal value for values

between 1 and 255.

A value of 0 disables the clock.

0x00: Clock disabled

0x01: Ref clk/1

0xFF: Ref clk/255

Values after reset are low (all 8 bits).

(MMC_SPI[0])

MMC card w/SPI protocol select

(MMC_CON:Mode=11)

MMC/SD Host Controller

(only active during a valid

command to a MMC/SD

card using MMC or SPI

protocol when MMC_CONN:

Mode=00 or11)

(only active during a valid

SPI transfer to a non-MMC

card when MMC_CON:

MPU Public Peripherals