Interrupt Generation - Texas Instruments OMAP5910 Technical Reference Manual

5.3.7

Interrupt Generation

Each DMA physical channel can generate an interrupt to the processor to
reflect the transfer status. Each DMA physical channel has a dedicated inter-
rupt line to the processor. All the DMA interrupts are level interrupts.
For every DMA logical channel, the following interrupt sources can be
programmed:
-
End of block: The last byte of the transfer has been written in destination.
-
End of frame: The last byte of the current frame has been written in
destination.
-
Half of frame: The middle byte of the current frame has been written in
destination.
-
Start of last frame: The first word of the last frame has been written in
destination.
-
DMA request collision: A new DMA request occurred before the end of
service of the previous one.
-
Time-out: An access has been timed out.
To prevent a definitive lock by a channel on a memory location or peripher-
al, all the DMA ports to memory/peripheral requests are monitored by a
time-out counter in the following sequence:
1) When the request is sent by the DMA to transfer data in a channel, a
time-out counter is triggered.
2) The request is acknowledged, and the time-out counter is stopped.
3) If the time-out counter reaches its threshold before the request is
acknowledged, the request is discarded and an error is reported in the
DMA channel by setting the relevant bit in DMA_CSR (channel status
register) and sending an interrupt to the processor. The channel is
stopped.
The time-out information is generated in the resources accessed by the
DMA:
J
System IMIF/local bus port: Time-out is signaled by the IMIF or the
local bus.
J
System TI peripheral bus port: Time-out is signaled by the TIPB
bridge.
J
System EMIFS/EMIFF port: Time-out is signaled by the EMIFS/
EMIFF (or traffic controller).
Generic Channels
System DMA Controller 5-23