Receive Control Register 1 Configuration (Dsp_Write(0X0000) => Rcr1); Receive Control Register 2 Configuration (Dsp_Write(0X0000) => Rcr2) - Texas Instruments OMAP5910 Technical Reference Manual

McBSP3
9.4.4.3 Receive Control Register Configuration
Table 9–17. Receive Control Register 1 Configuration (DSP_Write(0x0000) => RCR1)
Bit Config Value
15 0b
14–8 000 0000b
7–5 000b
4–0 0 0000b
Table 9–18. Receive Control Register 2 Configuration (DSP_Write(0x0000) => RCR2)
Bit Config Value
15 0b
14–8 000 0000b
7–5 000b
4–3 00b
2 0b
1–0 00b
9-18
The values of RWDLEN1, 2 and XWDLEN1, 2 must be set to the same value
in SPI mode.
DSP_Write(0x0000) => RCR1; set up RCR1 per below configuration.
Description
Reserved
Set receive frame length as one word per frame
Set receive word length as 8 bits per frame
Reserved
DSP_Write(0x0000) => RCR2; set up RCR2 per below configuration.
Description
Set single-phase frame
Don't care for single phase frame
Don't care for single phase frame
Set no companding data and transfer start with MSB first
Set FSR not ignore after the first resets the transfer
Set data delay as 0 bit