System Operating Details - Texas Instruments OMAP5910 Technical Reference Manual

3.10 System Operating Details

3.10.1 DSP Private Peripherals
3.10.2 DSP Public Peripherals
The DSP private peripherals are connected to the DSP CPU by a private TIPB
bridge. This provides reduced latency for DSP access to these particular
peripherals. The private peripherals consist of the following modules, which
are described in detail in Chapter 8, DSP Private Peripherals.
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Three general-purpose timers
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A watchdog timer
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An interrupt handler
These modules are clocked by dedicated signals controlled by the CLKM2
DSP_CKCTL register.
The access rate to these peripherals is fixed by the TIPB bridge module and
does not have to be user-configured.
The public TIPB connects the DSP public peripherals to the DSP CPU to pro-
vide a flexible communications scheme where the DSP or MPU domains can
access these devices. Because the peripheral registers are also mapped in
the MPU memory space, the MPU domain can access these peripherals indi-
rectly via the MPUI and public TIPB bridge. This results in a pseudodynamic
sharing scheme. The DSP public peripherals consist of the following modules,
which are described in detail in Chapter 9, DSP Public Peripherals:
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Two McBSPs—McBSP1 and McBSP3
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Two MCSIs—MCSI1 and MCSI2
These peripherals are clocked by the DSPXOR_CK signal, which is a buffered
version of the OMAP5910 CLKIN signal.
The access rate to these peripherals is configured by strobe 2 control bits in
the DSP TIPB CMR register. See Section 3.5.1, Control Mode Register.
System Operating Details
DSP Subsystem 3-39