MCSI2
9.7 MCSI2
9.7.1
MCSI2 Pin Description
Table 9–41. MCSI2 Pin Descriptions
Pin
MCSI2.DIN
MCSI2.DOUT
MCSI2.CLK
MCSI2.SYNC
9.7.2
MCSI2 Interrupt Mapping
Table 9–42. MCSI2 Interrupt Mapping
9.7.3
MCSI2 DMA Request Mapping
Table 9–43. DMA Request Mapping—MCSI2
9-54
This section provides information specific to MCSI2 (Figure 9–30) on the
OMAP5910 device.
Table 9–41 identifies the MCSI2 I/O pins.
I/O Direction
In
Out
In/out
In/out
Table 9–42 identifies the MCSI2 interrupts. MCSI2 generates level 2 interrupts
for both the DSP and the MPU. Only one MPU MCSI2 interrupt covers TX, RX,
and frame error conditions; software must check the MCSI2 status register to
determine the interrupt source.
Incoming Interrupts
MCSI2 TX interrupt
MCSI2 RX interrupt
MCSI2 Frame Error
Table 9–43 identifies MCSI2 DMA request lines. Only the DSP DMA controller
can transfer MCSI2 data; there is no MPU DMA capability.
DMA Request Source DMA Request Line—DSP DMA Request Line—MPU
MCSI2 TX
MCSI2 RX
Description
Data input
Data output
Bit clock
Frame synchronization
Level 2 DSP Interrupt
IRQ_08
IRQ_09
IRQ_11
DMA_REQ_03
DMA_REQ_04
Level 2 MPU Interrupt
IRQ_17
IRQ_17
IRQ_17
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