Memory Interfaces - Texas Instruments OMAP5910 Technical Reference Manual

Memory Interfaces

4.3 Memory Interfaces
4.3.1 Internal Memory Interface
4.3.1.1 IMIF Priority Handler
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The TC has three memory interfaces:
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Internal memory interface (IMIF)
-
External memory interface slow (EMIFS)
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External memory interface fast (EMIFF)
The IMIF interfaces to an internal 192K-byte block of SRAM. The interface
handles all single and burst requests from the MPU, the C55x DSP, the system
DMA engine, and the local bus.
This memory interface has two software-selectable priority algorithms for
resolving simultaneous access requests: least recently used and dynamic
priority. The priority scheme is shared with the EMIFS and EMIFF and is set
in the OMAP5910
FUNC_MUX_CTRL_0). See Chapter 6, MPU Private Peripherals, for details
on configuration registers.
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Least recently used
J
A round-robin arbitration scheme. The highest priority requestor is the
one that least recently accessed the memory.
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Dynamic priority
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Dynamic priority uses high- and low-priority queues.
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Each requestor, except the MPU, has a time-out register allocated to it
(see Time-Out Registers in Section 4.4). These registers hold the
number of clock cycles that a low-priority queue request must wait
before it is moved from the low-priority queue to the high-priority
queue.
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At reset, all requestors are initially in the low-priority queue and the
time-out registers are set to minimum value for each requestor. You
must program these registers before using dynamic priority.
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The low-priority queue order is:
H
MPU
H
DSP
H
Local bus
H
DMA (all channels including LCD)
configuration registers (bit 20, LRU_SEL in