Tc Block Diagram; Introduction - Texas Instruments OMAP5910 Technical Reference Manual

Introduction

4.1 Introduction
Figure 4–1. TC Block Diagram
OMAP5910
32
E
Flash and M
16
SRAM I
memories F
S
E
16 M
Memory interface
SDRAM
I
traffic controller (TC)
memories
F
F
I
M
I
F
32
32
SRAM
1.5M Bits
JTAG/
Emulation
I/F
4-2
The memory interface traffic controller (TC) manages all accesses by the
MPU, the TMS320C55x DSP, the system DMA, and the local bus to the
OMAP5910 system memory resources (SRAM, SDRAM, flash, ROM, etc.).
The TC also manages accesses by the MPU or the USB host. The USB host
is an internal OMAP5910 peripheral connected on the local bus, so the TC
contributes in managing USB host accesses.
Figure 4–1 shows the OMAP5910 device with the traffic controller highlighted.
Figure 4–2 shows the traffic controller in more detail. Table 4–1 lists the
access modes and data access width of the controllers (MPU, C55x DSP,
system DMA, and local bus).
TMS320C55x DSP
(Instruction Cache, SARAM,
DSP DARAM, DMA,
32
MMU H/W accelerators)
32
MPU Bus
32
32
32
System
DMA
32
controller
MPU Core
16
(TI925T)
(Instruction
Cache, Data
Clock and reset management
Cache, MMU)
LCD
I/F
OSC
ETM9
12 MHz
DSP private
Private peripherals
peripheral bus
16
Interrupt handlers
DSP public (shared) peripheral bus
16
16
MPU
interface
32
MPU
peripheral
32
bridge
32
MPU Private Peripheral Bus
32
MPU private peripherals
Level 1/2 interrupt handlers
OSC Configuration registers
Device identification
Reset External clock
Clock
32 kHz
requests
DSP
Timers (3)
DSP public peripherals
Watchdog timer
Level 1/2
McBSP1
McBSP3
MCSI1
MCSI2
MPU/DSP shared peripherals
TIPB
switch
UART3 IrDA
MPU public peripherals
McBSP2
USB host I/F
MPU public
peripheral bus
USB function I/F
2
I C
µωιρε
Camera I/F
MPUIO
32-kHz timer
PWT
PWL
Keyboard I/F
MMC/SD
LPG x2
Frame adjustment
counter
Timers (3)
HDQ / 1-WIRE
Watchdog timer
RTC
Mailbox
GPIO I/F
UART1
UART2