Clock Generation And System Reset Management - Texas Instruments OMAP5910 Technical Reference Manual

Introduction
2.1 Introduction
2-2
The MPU of the OMAP5910 device controls the memory management units
(MMUs), the system direct memory access (DMA) controller, the MPU TI
peripheral bus (TIPB) bridge, and peripherals.
Figure 2–1 shows the OMAP5910 device with the MPU subsystem high-
lighted. The subsystem contains the following components:
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MPU core (see Section 2.2, MPU Core)
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Traffic controller (see Chapter 4, Memory Interface Traffic Controller)
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MPU MMU (see Section 2.7, MPU Memory Management Unit)
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DSP MMU (see Section 2.8, DSP Memory Management Unit)
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System DMA controller (see Chapter 5, System DMA Controller)
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LCD controller (see Chapter 11, LCD Controller)
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MPU TIPB bridge (see Section 2.10, MPU TI Peripheral Bus Bridges)
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Clock manager (see Chapter 15, Clock Generation and System Reset
Management)
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Interrupt handler (see Section 6.4.1, MPU Level 1 Interrupt Handler,
Section 6.4.2, MPU Level 2 Interrupt Handler, and Section 8.4, [DSP]
Interrupt Handlers)
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Timers (see Section 6.2, [MPU] Timer Description and Section 8.2, [DSP]
Timers)
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Watchdog timer (see Section 6.3, [MPU] Watchdog Timer and Section 8.3,
[DSP] Watchdog Timer)
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Interprocessor communication
Communication)
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1.5M-bit SRAM internal memory
(see Section 10.2, Interprocessor