DSP DMA
Figure 76.
Functional Multiplexing DSP DMA Register A (FUNC_MUX_DSP_DMA_A)
31
30
Reserved
RW-0
24
CONF_DSP_DMA_EVT_05
RW-0x04
14
7
CONF_DSP_DMA_EVT_02
RW-0x01
Note:
R = Read; W = Write; −n = Value after reset; −x = Value after reset is not defined.
Table 54. Functional Multiplexing DSP DMA Register A (FUNC_MUX_DSP_DMA_A)
Field Descriptions
Bits
Field
31−30 Reserved
29−25 CONF_DSP_DMA_
EVT_06
24−20 CONF_DSP_DMA_
EVT_05
19−15 CONF_DSP_DMA_
EVT_04
14−10 CONF_DSP_DMA_
EVT_03
150
DSP Subsystem
29
20
CONF_DSP_DMA_EVT_03
RW-0x02
5
4
Value
Description
These read-only bits return 0s when read.
0−27
Configuration bits for DMA event 6. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
6. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 5. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
5. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 4. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
4. The value n must be between 0 and 27.
0−27
Configuration bits for DMA event 3. Writing a value n to this
register maps peripheral request source n+1 to DSP DMA event
3. The value n must be between 0 and 27.
CONF_DSP_DMA_EVT_06
RW-0x05
19
CONF_DSP_DMA_EVT_04
RW-0x03
10
CONF_DSP_DMA_EVT_01
RW-0x00
25
15
9
8
CONF_DSP_DMA_
EVT_02
RW-0x01
0
SPRU890A