Dsp External Memory Space; I/O Memory Space - Texas Instruments OMAP5910 Reference Manual

DSP Subsystem Memory
3.2

DSP External Memory Space

3.3

I/O Memory Space

28 DSP Subsystem
The DSP core and DMA controller use the external memory interface (EMIF)
to access the DSP external memory. External memory for the DSP subsystem
ranges from byte address 0x02 8000 to 0xFF 8000 if the internal PDROM is
enabled, or to 0xFF FFFF if the PDROM is not enabled. See Figure 18 for more
details.
Note:
The term DSP external memory refers to memory outside of the DSP
subsystem internal memory space. This includes program addresses in the
range of 0x02 8000 to 0xFF 8000 if the internal PDROM is enabled, or to
0xFF FFFF if the PDROM is not enabled.
All DSP external memory access requests are passed through the DSP
memory management unit (MMU). If this unit is enabled and configured by the
MPU core, it translates the DSP external memory access request address,
also called a virtual address, into a system memory address, also called a
physical address, that is then passed to the traffic controller. The traffic
controller completes the memory access through one of the three system
memory interfaces: internal memory (IMIF), slow external memory (EMIFS),
or fast external memory (EMIFF).
If the MMU is not enabled, then the access request is passed directly to the
system traffic controller. In this case, the DSP virtual address is mapped to the
first 16M bytes of chip select space 0 (CS0) of the system memory.
The DSP subsystem I/O space is a separate address space from the
data/program memory space. Configuration and data registers for all
peripherals reside in the DSP subsystem I/O space, which consists of
64K-word addresses. Each peripheral maps into a 1K-word section of I/O
memory.
OMAP devices include sets of peripherals grouped into three main categories:
shared, public, or private.
DSP/MPU shared peripherals are connected to both the MPU public
-
peripheral bus and the DSP public peripheral bus. Connections are routed
through a TI peripheral bus switch, which must be configured to allow MPU
domain or DSP domain access. Some shared peripherals have
permanent connections to both public peripheral buses, although read
and write accesses to each peripheral register may differ.
SPRU890A