Level 1 And Level 2 Omap5910 Mpu Interrupt Mapping - Texas Instruments OMAP5910 Technical Reference Manual

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6.5 Level 1 and Level 2 Interrupt Mapping
Table 6–16. Level 1 and Level 2 OMAP5910 MPU Interrupt Mapping
Incoming Interrupts
Level 2 interrupt handler IRQ
Camera interrupt
Reserved
External FIQ
McBSP2 TX interrupt
McBSP2 RX interrupt
IRQ_RTDX
IRQ_DSP_MMU_ABORT
IRQ_HOST_INT
IRQ_ABORT
IRQ_DSP_MAILBOX1
IRQ_DSP_MAILBOX2
Reserved
IRQ_TIPB_BRIDGE_PRIVATE
IRQ_GPIO
IRQ_UART3
IRQ_TIMER3
IRQ_LB_MMU
Reserved
IRQ_DMA_CH0_CH6
IRQ_DMA_CH1_CH7
IRQ_DMA_CH2_CH8
† IRQ_RTDX is used in emulation for the Code Composer Studio RTDX (real time data exchange) interrupt.
Table 6–16 lists the mapping of the incoming interrupts.
IRQ_ABORT (IRQ_9) is the traffic controller abort IRQ. It is also connected to
DSP IRQ_12. This interrupt comes from either a TIPB bus or the MPUI and
is caused by a time-out abort.
Configuration
Level 1 and Level 2 Interrupt Mapping
Default
Sensitivity
Interrupt Line
on Level 1
Level
Level
Edge
Edge
Edge
Level
Level
Level
Level
Level
IRQ_10
Level
IRQ_11
Level
IRQ_13
Level
IRQ_14
Level
IRQ_15
Edge
IRQ_16
Level
IRQ_17
Level
IRQ_19
Level
IRQ_20
Level
IRQ_21
MPU Private Peripherals
Interrupt Line
on Level 2
IRQ_0
IRQ_1
IRQ_2
IRQ_3
IRQ_4
IRQ_5
IRQ_6
IRQ_7
IRQ_8
IRQ_9
6-17

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