Cp15 Registers Or Functions Used By The Mmu; Mmu Program-Accessible Registers - Texas Instruments OMAP5910 Technical Reference Manual

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Table of Contents

MPU Memory Management Unit

Table 2–16. CP15 Registers or Functions Used by the MMU

Address Translation

The system control coprocessor (CP15) registers listed in Table 2–16, in con-

junction with the translation tables stored in memory, determine the operation

of the MMU or hold the MMU state for access by the processor.

Control register

Translation table base

Domain access control

Fault status

Fault address

TLB operations

TLB lock operation

All of these registers (except register 8) contain state and can be read from and

written to. The MMU also updates registers 5 and 6 upon a data abort to record

the cause and address of the abort (see Section 2.6, Coprocessor 15 for more

details on CP15).

Translation information, which consists of both the address translation data

and the access permission data, resides in a translation table located in physi-

cal memory. The MMU provides the logic needed to traverse this translation

table, obtain the translated address, and check the access permission.

There are four routes by which the address translation (hence access permis-

sion) takes place. The route taken depends on whether the address in ques-

tion has been marked as a section-mapped access or a page-mapped access.

There are three sizes of page-mapped access (large, small, and tiny pages).

However, the translation process always starts out in the same way, as

described below, with a level 1 fetch. A section-mapped access only requires

a level 1 fetch, but a page-mapped access also requires a level 2 fetch.