Instruction Cache - Texas Instruments OMAP5910 Technical Reference Manual

2.3 Instruction Cache

2.3.1 Operation
2.3.2 Validity
The 16K-byte instruction cache (I-cache) has 1024 lines of 16 bytes arranged
as a two-way set-associative cache. It uses the virtual addresses generated
by the processor core. The I-cache is always reloaded one line at a time. It can
be enabled or disabled via the CP15 control register (I_CP15 bit) and is
disabled and flushed upon reset.
Disabling the I-cache does not invalidate it.
You can enable the I-cache independently from the MMU.
When the I-cache is enabled, it is searched whenever the processor requests
an instruction. If the cache hits, data is returned to the core whether the MMU
is enabled or not. If a cache read misses, a line fetch is performed and data
is written to the cache following a least recently used (LRU) replacement algo-
rithm. For best performance, enable the I-cache as soon as possible after
reset. If the I-cache is disabled, it is not searched. All instruction fetches
generate a single 16-bit or 32-bit external access. An instruction miss
generates line load.
The flush I-cache instruction is fetched at cycle time 0, for example, but not
executed until cycle time 4 (the TI925T uses a five-stage opcode pipe). Thus,
four additional opcodes potentially are still fetched from the I-cache before the
flush I-cache opcode is executed. Once executed, the entire I-cache is invali-
dated before the next opcode executes. Typically, four non-opcodes following
the CP15 instruction flush the cache to avoid confusion.
The I-cache content is not flushed when the I-cache is disabled. Its contents
remain valid and are accessible again when the I-cache is reenabled.
Instruction Cache
MPU Subsystem 2-5